1. Field of the Invention
This invention relates to a driving circuit for a display device, and more particularly to a liquid crystal display (LCD) device having a shift register configured with amorphous silicon thin film transistors.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) used as a display device for a television or a computer controls light transmittance of a liquid crystal using an electric field to thereby display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix configuration, and a driving circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, gate lines and data lines are arranged in such a manner to cross each other. A liquid crystal cell is positioned at each area defined by the gate lines and the data lines. The liquid crystal display panel is provided with pixel electrodes and a common electrode for applying an electric field to each liquid crystal cell. Each of the pixel electrodes is connected to any one of the data lines, via the source and drain terminals of a thin film transistor (TFT), which serves as a switching device. The gate terminal of the TFT is connected to any one of the gate lines.
The driving circuit includes a gate driver for driving the gate lines, and a data driver for driving the data lines. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel. The data driver applies a video signal to each data line whenever the scanning signal is applied to any one of the gate lines. Thus, the LCD controls light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with a video signal for each liquid crystal cell, thereby displaying a picture.
In such a driving circuit, the gate driver generates a scanning signal for sequentially driving the gate lines using a shift register. The data driver, which also includes a shift register, generates a sampling signal for sequentially sampling video signals inputted from the exterior thereof.
FIG. 1 is a block diagram illustrating a configuration of a general two-phase shift register.
Referring to FIG. 1, the shift register includes 1st to nth stages connected in cascade. The 1 st to nth stages are commonly supplied with first and second clock signals C1 and C2 along with high-level and low-level driving voltages VDD and VSS, and are supplied with a start pulse Vst or an output signal of the previous stage. The 1st stage outputs a first output signal Out1 in response to the start pulse Vst and the first and second clock signals C1 and C2. The 2nd to nth stages output 2nd to nth output signals, respectively, in response to the output signal of the previous stage and the first and second clock signals C1 and C2. The 1st to nth stages have an identical circuit configuration, and sequentially shift a specific voltage of the start pulse Vst. The 1st to nth output signals Out1 to Outn are supplied as a scanning signal for sequentially driving the gate lines of the liquid crystal display panel, or as a sampling signal for sequentially sampling a video signal within the data driver.
FIG. 2 shows a detailed circuit configuration of one stage of the shift register illustrated in FIG. 1.
In FIG. 2, the stage includes a fifth NMOS transistor T5 for outputting a first clock signal C1 to an output line under control of a Q node, a sixth NMOS transistor T6 for outputting a low-level driving voltage VSS under control of a QB node, and first to fourth NMOS transistors T1 to T4 for controlling the Q node and the QB node.
Such a stage is supplied with the high-level and low-level voltages VDD and VSS, and with the start pulse Vst and the first and second clock signals C1 and C2, as illustrated in FIG. 3. Herein, the second clock signal C2 is a signal in which a high-state voltage and a low-state voltage each having certain pulse width are alternately supplied, whereas the first clock signal C1 is a signal having a voltage opposite to the second clock signal C2. A high state of the start pulse Vst is synchronized with a high state of the second clock signal C2. The start pulse Vst is a signal supplied from the exterior or an output signal of the previous stage.
Hereinafter, an operation procedure of the stage will be described with reference to driving waveforms illustrated in FIG. 3.
In a period of ‘A’, the first NMOS transistor T1 is turned on by a high-state second clock signal C2 to thereby apply a high-state voltage of the start pulse Vst to the Q node, that is, pre-charge it thereto. The high-stage voltage pre-charged to the Q node turns on the fifth NMOS transistor T5 to thereby apply a low-state voltage of the first clock signal to the output line. At this time, the second NMOS transistor T2 also is turned on by said high-state second clock signal to thereby apply a high-level driving voltage VDD to the QB node. Then, the high-level driving voltage VDD supplied to the QB node turns on the sixth NMOS transistor T6 to thereby supply a low-level driving voltage VSS. Thus, in the ‘A’ period, the output line of the stage outputs a low-state output signal OUT.
In a period of ‘B’, the first NMOS transistor T1 is turned off by a low-state second clock signal C2 to thereby float the Q node into a high state. Thus, the fifth NMOS transistor T5 maintains a turn-on state. At this time, as the first clock signal C1 has a high-state voltage, the floated Q node is boot-strapped by an effect of an internal capacitor Cgs provided between the gate and the drain of the fifth NMOS transistor T5 and a capacitor CB. Accordingly, a voltage at the Q node is further increased to continuously turn on the fifth NMOS transistor T5, thereby rapidly supplying a high-state voltage of the first clock signal C1 to the output line. Further, the Q node floated into a high state turns on the fourth NMOS transistor T4 and a high-state first clock signal C1 turns on the third NMOS transistor T3 to supply the low-level driving voltage VSS to the QB node, thereby turning off the sixth NMOS transistor T6. Thus, in the ‘B’ period, the output line of the stage outputs a high-state output signal OUT.
In a period of ‘C’, the first NMOS transistor T1 is turned on by a high-state second clock signal C2 to supply a low-state voltage of the start pulse Vst to the Q node, thereby turning off the fifth NMOS transistor T5. At this time, the second NMOS transistor T2 is turned on by a high-state second clock signal C2 to supply the high-level driving voltage VDD to the QB node, thereby turning on the sixth NMOS transistor T6 to output the low-level driving voltage VSS to the output line. At this time, the third NMOS transistor T3 is turned off by a low-stage first clock signal C1 and the fourth NMOS transistor T4 is turned off by the low-state Q node, thereby maintaining the high-level driving voltage VDD at the Q node. Thus, in the ‘C’ period, the output line of the stage outputs a low-state output signal OUT.
In a period of ‘D’, the second NMOS transistor T2 is turned off by a low-state second clock signal C2 and the fourth NMOS transistor T4 is turned off by the low-state Q node, thereby floating the QB node with the high-level driving voltage VDD supplied in the previous period ‘C’, even though the third NMOS transistor T3 is turned on by a high-state first clock signal C1. Thus, the sixth NMOS transistor T6 maintains a turn-on state to thereby output the low-level driving voltage VSS to the output line. As a result, in the ‘D’ period, the output line of the stage outputs a low-state output signal OUT.
In the remaining periods, the ‘C’ and ‘D’ periods are alternately repeated, so that the output signal OUT of the stage continuously maintains a low state.
Recently, various attempts have been made to apply a polycrystalline silicon TFT technique, which can directly form a shift register on a glass substrate, to display devices. However, when the shift register of a display device is configured with amorphous silicon TFTs, some characteristics of the output signal OUT such as the rising time and falling time thereof, etc. are poor due to a parasitic capacitor Cgs existing in the interior of the thin film transistors. In order to solve this, a scheme of enlarging the channel width of the amorphous TFTs has been suggested. However, the enlarged channel width of the amorphous TFTs creates a high turn-off leakage current, which distorts the output signal of the shift register and makes it difficult for the shift register to maintain a low state. More particularly, the voltage at the QB node in the ‘D’ period, which is floated into a high state, becomes unstable because of the high leakage current of the amorphous silicon TFT having an enlarged channel width. Therefore, the sixth NMOS transistor T6 requiring maintaining a turn-on state becomes also unstable, thereby distorting a low state of the output signal OUT.